Anna University
DIGITAL LOGIC CIRCUITS
Department of Electrical and Electronics Engineering
4th Semester
Part B Important Questions for May/June 2013
UNIT -1
1. Problem from Quine Mc-Cluskey method (16)
2. Problem from Code converters (16)
3. Design (or) implementation of multiplexer ,de-multiplexer circuits (each 8)
4. Problem from designing the combinational circuits. (16)
5. Problem from simplification and implementation of SOP and POS functions using gates (8)
Unit II
1. Problems from realisation of SR,D,T,JK flip flops (8)
2. Problems from analysis of synchronous sequential circuits (16)
3. Problems from design of synchronous sequential circuits using flip flop(16)
4. Design of counters (12)
Unit III
1. Problems of analysis of asynchronous sequential circuits (16)
2. Problems of design of asynchronous sequential circuits (16)
Unit IV
1. Draw the TTL inverter circuits (12)
2. Explain the working of 2 input and 3 input TTL totem pole NAND gate .(16)
3. Explain the concept of concept ,operation and characteristics of CMOS family. Draw the circuit of CMOS two input NAND gate and explain its operation (16)
4. Draw the circuit of CMOS using NAND and NOR gates (6)
5. Write a note on ROM and its type (16)
6. Problem from designing a ROM circuits (8)
7. Problem from implementing the Boolean function with the PLA (12)
Unit V
1. explain the design procedure of RTL design using VHDL (16)
2. write the note on test benches and its types (8)
3. program using VHDL code can be asked (16)
(example : mod 16, full adder, half adder, counters, multiplexers, de-multiplexer etc.)